1. Field of the Invention
The present invention relates to semiconductor fabrication processes and, more particularly, to dry develop processes with improved tunability of critical dimensions during semiconductor fabrication.
2. State of the Art
A common process requirement in semiconductor device fabrication is the removal of material layers or films to form features of a semiconductor device. For example, semiconductor fabrication may include the etching and formation of structures and openings such as trenches, contacts and vias in the material layers overlying conductive or semiconductive substrates. The patterning and formation of such structures is generally accomplished through the use of a patterned photolithographic mask and often, a hard mask or resist.
During semiconductor fabrication, it is preferable for sidewalls of the mask and resist used to define desired features to remain perpendicular to the surface of the underlying substrate. However, as feature dimensions are ever-decreasing and desired feature densities are ever-increasing, it is more and more difficult to create complex circuit structures on a small size chip using conventional etching processes. For example, as the size of the photoresist or photomask patterns are reduced, the thickness of the photomask must also decrease, in order to control pattern resolution in the underlying layers. The thinner photomask is not very rigid and may be eroded away during the etching process, which may lead to sidewall bowing (i.e., concave sidewalls) in the photomask and to poor line and profile control, as well as loss of the critical dimension of the mask and underlying substrate.
One approach to solve this problem of mask erosion is to include an antireflective coating (ARC) beneath the photomask. The ARC is formed over the substrate layers to be etched to prevent non-uniform reflection of radiation during the patterning of the photomask and, thus, inhibit defects in the photomask. Subsequently, the ARC may be etched using the photomask layer as a mask to remove those layers of the ARC which correspond to the openings in the photomask. However, even with the use of an ARC, there may still be lateral etching and sidewall bowing using conventional etching processes.
In another approach to the mask erosion problem, a carbon-based mask may be formed above an underlying semiconductor substrate and beneath the photomask and/or ARC as an etch-stop layer in order to improve the fidelity of the masking layers during etching of the underlying substrate layers. The carbon-based mask is more rigid and etch resistant than the photomask layer, thus providing for good etch selectivity for fabrication of openings in the semiconductor device.
Conventional plasma dry etch gas chemistries include CHF3+CF4+O2+Ar, N2+He+O2, N2+O2, N2+He, O2+CO2, O2+SO2, and C2F6+Ar. This type of plasma etching is called a “dry develop” process. Dry develop process chemistries, such as O2+SO2, are known in the art and work well, as they give good selectivity to the mask material and the underlying layer. However, conventional dry develop process chemistries lack sufficient ability to tune the critical dimension (CD) of the mask by preferentially growing, trimming or slanting the sidewall profile of a carbon-based mask. Furthermore, when the critical dimension of the mask falls below 120 nm, it becomes advantageous or even necessary to use advanced patterning and etching techniques. The critical dimension of a mask includes the profile and dimensions of the features of a mask such as the dimensions of the patterned solid regions as well as the dimensions of the exposed and removed areas of the mask. For example, it may be advantageous to grow (i.e., add material to), to trim (i.e., remove material from) and/or slant a surface defining a critical dimension of the carbon-based mask and, as such, tune the critical dimension thereof.
Therefore, there is a need for a dry develop process providing the ability to tune and control critical dimensions of a carbon-based mask during the fabrication of semiconductor devices.